Yen and Ker : Effect of Iec - like Fast Transients on Rc - Triggered Esd Power Clamps

Four power-rail electrostatic-discharge (ESD) clamp 4 circuits with different ESD-transient detection circuits have been 5 fabricated in a 0.18-μm CMOS process to investigate their sus6 ceptibility against electrical fast-transient (EFT) tests. Under EFT AQ1 7 tests, where the integrated circuits in a microelectronic system 8 have been powered up, the feedback loop used in the power-rail 9 ESD clamp circuits may lock the ESD-clamping NMOS in a 10 “latch-on” state. Such a latch-on ESD-clamping NMOS will con11 duct a huge current between the power lines to perform a latchup12 like failure after EFT tests. A modified power-rail ESD clamp 13 circuit has been proposed to solve this latchuplike failure and to 14 provide a high-enough chip-level ESD robustness. 15